Signal processing apparatus, control method for signal processing apparatus, imaging apparatus recording/reproducing apparatus

ABSTRACT

An imaging system in which, if image data of variable resolutions is to be handled in keeping with the increasing resolution of the image data, the processing is executed efficiently without lowering the processing capability of the respective circuits. To this end, a memory controller  22  time-divisionally transmits an acknowledge signal to the respective circuits within a range of the bandwidth limitation of an image data bus  33  in which image data can be furnished to the respective circuits, and manages control so that the respective circuits will execute the pre-set processing. That is, the memory controller  22  has access to data in the respective circuits in real-time in actuality to cause image data to be written from the respective circuits to the image memory  32  or to be read out from the image memory  32  and sent to the respective circuits.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a signal processing device suitablyemployed in a still picture imaging device. More particularly, itrelates to a signal processing device that is able to performparticularly efficiently signal processing, a control method therefor,an imaging device and a recording/reproducing apparatus.

[0003] 2. Description of the Related Art

[0004] A digital still camera retrieves image data obtained by a CCDimage sensor into a DRAM or a flash memory and subsequently transfersthe image data to a so-called personal computer or the like. A majorproportion of this type of the digital still camera has so far been ofthe type coping with the video graphics array (VGA) system.

[0005] Referring to FIG. 1, this digital still camera 200 includes a CCDimage sensor 201 for generating image signals, an input processing/imageprocessing circuit 202, a memory controller 203 for reading and writingimage data, an output processing circuit 204 for conversion to an outputimage of a pre-set system, a finder 205 for displaying the state of anobject at the time of image shooting, a recording unit 207 for recordingcompressed image data over a CPU bus 206 and a compression/expansioncircuit 208 for compressing/expanding image data. The digital stillcamera 200 also includes a memory 209, formed by, for example, a DRAM,and a CPU 210 for controlling the overall device.

[0006] Before starting the image shooting of an object, the user has toconfirm an object image displayed on the finder 205. This state istermed a finder mode. At this time, the CCD image sensor 201 sends imagesignals obtained on photoelectric conversion to the inputprocessing/image processing circuit 202. The input processing/imageprocessing circuit 202 performs the correlated dual sampling processingon the image signals to digitize the image signals. The inputprocessing/image processing circuit 202 then performs pre-set signalprocessing, such as gamma correction, knee processing or cameraprocessing and routes the processed image signals to the memorycontroller 203, which then is responsive to the control by the CPU 210to send the image data from the input processing/image processingcircuit 202 to the output processing circuit 204. The output processingcircuit 204 encodes image data in accordance with, for example, theNational Television System Committee (NTSC) system, and analogizes theencoded image data to route the resulting analog data to the finder 205.This allows the object as an object of image shooting to be indicated onthe finder 205.

[0007] On the other hand, if the user pushes a shutter button, notshown, to shift to the recording mode, the memory controller 203 causesthe image data furnished from the input processing/image processingcircuit 202 to be written in the memory 209. The CPU 210 causes theimage data to be read out from the memory 209 and compresses the imagedata from the recording unit 207 in the compression/expansion circuit208 with compression in accordance with, for example, the Jointphotographic Experts Group (JPEG) system to record the compressed imagedata in the recording unit 207.

[0008] If the user performs pre-set processing to shift to thereproducing mode, the CPU 210 causes image data to be read out from therecording unit 207 to cause the image data to be expanded in JPEG systemin the compression/expansion circuit 208 to route the resulting data viamemory controller 203 and output processing circuit 204 to the finder205. This causes the as-shot image to be displayed on the finder 205.

[0009] In keeping up with recent outstanding technical progress in theCCD image sensor, the resolution of image data is nearly surpassing1,000,000 pixels. On the other hand, it may be feared that the digitalstill camera of the above-described structure cannot sufficiently copewith the image data exceeding 1,000,000 pixels.

[0010] If, for example, the CCD image sensor 201 outputs image signalsof high resolution, the input processing/image processing circuit 202,memory controller 203 or the output processing circuit 204 cannotprocess image data in real-time, such that the delay of, for example,one second is liable to be produced until an image of the object isdisplayed on the finder 205. This incurs an inconvenience in shooting animage of object even if the object makes the slightest movement.

[0011] Moreover, since the accessing to image data which needs to be inreal-time and data accessing by the CPU 210 with indefinite data rateare performed on a common bus, the real-time accessing is difficult torealize if the image data is increased in volume, thus causing the CPUbus to be stagnant to lower the processing ability of the respectivecircuits.

SUMMARY OF THE INVENTION

[0012] It is therefore an object of the present invention to provide asignal processing method and apparatus in which, even if image data ofvarious different image data are handled in keeping with increasedresolution of image data, the processing can be executed efficientlywithout lowering the processing capability of the respective circuits.

[0013] In one aspect, the present invention provides a signal processingapparatus including storage means for storing image data, control meansfor controlling the writing/readout of the image data for the storagemeans and a plurality of signal processing means for processing theimage data in a pre-set fashion and for outputting to the control meansa request signal for demanding furnishment of the image data for thesignal processing or demanding the outputting of the processed imagedata. The control means manages control on furnishment of the requestsignal to select one or more of the signal processing means which hasoutputted the request signal, to furnish the image data read out fromthe storage means to the selected signal processing means or to writethe image data outputted by the selected signal processing means in thestorage means.

[0014] In another aspect, the present invention provides a controllingmethod for a signal processing apparatus adapted fortransmitting/receiving image data between a plurality of signalprocessing means and storage means for storing image data, the signalprocessing means being adapted for processing the image data in apre-set fashion and for outputting to the control means a request signalfor demanding furnishment of the image data for signal processing ordemanding the outputting of the processed image data. The controllingmethod includes selecting, on furnishment of the request signal from theplural signal processing means, one or more of the signal processingmeans which has outputted the request signal, and furnishing the imagedata read out from the storage means to the selected signal processingmeans or writing the image data outputted by the selected signalprocessing means in the storage means.

[0015] In still another aspect, the present invention provides animaging apparatus including imaging means, storage means for transientlystoring image data from the imaging means, control means for controllingthe writing/readout of the image data for the storage means, a pluralityof signal processing means for processing the image data in a pre-setfashion and for outputting to the control means a request signal fordemanding furnishment of the image data for signal processing ordemanding the outputting of the processed image data, and outputtingmeans for outputting image data processed by the signal processingmeans. The control means manages control on furnishment of the requestsignal to select one or more of the signal processing means which hasoutputted the request signal to furnish the image data read out from thestorage means to the selected signal processing means or to write theimage data outputted by the selected signal processing means in thestorage means.

[0016] In yet another aspect, the present invention provides arecording/reproducing apparatus including imaging means, inputprocessing means for performing pre-set input processing on image datafrom the imaging means, display processing means for displaying imagedata on display means, first storage means for transiently storing theimage data from the imaging means, control means for controlling thewriting/readout of the image data for the first storage means,resolution converting means for converting the resolution of image data,compression/expansion means for compressing/expanding the image data andrecording/reproducing controlling means for causing the compressed imagedata to be recorded on second storage means and for causing the imagedata recorded on the second storage means to be reproduced. The controlmeans selects one or more signal processing means from the inputprocessing means, display processing means, resolution converting meansand the compression/expansion means. The control means causes the imagedata read out from the first storage means to be sent to the selectedsignal processing means or causes the image data outputted by theselected signal processing means to be written in the first storagemeans.

[0017] In the signal processing apparatus and the control methodtherefor, according to the present invention, if a request signal issent from each signal processing means, the signal processing meanswhich has outputted the request signal having the utmost priority in thepriority order is selected. Control is then performed for supplying theimage data read out from the storage means over the image data bus tothe selected signal processing means, or writing the processed imagedata of the selected signal processing means over the image data bus tothe storage means, so that efficiently signal processing will beexecuted in the respective signal processing means.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a block diagram for illustrating the structure of aconventional digital still camera.

[0019]FIG. 2 is a block diagram showing a schematic structure of adigital still camera embodying the present invention.

[0020]FIG. 3 is a block diagram showing the schematic structure of thedigital still camera shown in FIG. 2.

[0021]FIG. 4 is a block diagram for illustrating flow of image data in asignal processing unit of the digital still camera shown in FIG. 2.

[0022]FIG. 5 is a block diagram for illustrating the structure of asimplified resolution conversion circuit in an input processing circuitof the signal processing unit.

[0023]FIG. 6 is a block diagram showing the structure of the resolutionconversion circuit of the signal processing unit.

[0024]FIG. 7 is a block diagram showing a specified structure of ahorizontal direction buffer, a horizontal direction conversionprocessing circuit, a vertical direction buffer and a vertical directionconversion processing circuit of the resolution conversion circuit.

[0025]FIG. 8 is a block diagram showing an alternative structure of theresolution conversion circuit.

[0026]FIG. 9 is a block diagram showing the structure of the verticaldirection buffer of the resolution conversion circuit.

[0027]FIG. 10 illustrates a technique for reading out image data fromthe image memory by the memory controller.

[0028]FIG. 11 illustrates the coordinate position of pixels making up animage.

[0029]FIG. 12 illustrates another technique for reading out image datafrom the image memory by the memory controller.

[0030]FIG. 13 is a block diagram showing the structure of the horizontaldirection buffer of the resolution conversion c constituted by a linebuffer.

[0031]FIG. 14 illustrates the technique when the memory controller readsout image data from the image memory.

[0032]FIG. 15 is a block diagram showing the structure of the simplifiedresolution conversion circuit in the NTSC/PAL encoder of the signalprocessing unit.

[0033]FIGS. 16A to 16F show a timing chart for illustrating the contentsof the signal processing in the respective circuits in the finder mode.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Referring to the drawings, preferred embodiments of the presentinvention will be explained in detail.

[0035] The present invention is applied to digital still camera 1,configured as shown for example in FIG. 2.

[0036] The digital still camera 1 includes an image generating unit 10for generating image signals, an input signal processor 20 forprocessing image data in a pre-set fashion, an image memory 32,comprised of an SDRAM, and a controller 40 for controlling the inputsignal processor 20.

[0037] The image generating unit 10 includes a solid-state imagingdevice for generating image signals, such as a CCD image sensor 11, asample holding-analog/digital circuit (S/H-A/D circuit 12) forsample-holding and digitizing the image signals to output image data,and a timing generator 13 for generating timing signals. This timinggenerator 13 generates horizontal synchronization signals and verticalsynchronization signals for controlling respective circuits of the imagegenerating unit 10 based on synchronization signals supplied from thesignal processor input.

[0038] The CCD image sensor 11 generates image data corresponding to XGA(extended graphic array: 1024×768) pixel data made up of, for example,800,000 pixels. The CCD image sensor 11 is driven based on thesynchronization signals from the timing generator 13 to output imagesignals at a rate of 30 frames per second. Meanwhile, the CCD imagesensor 11 has the function of thinning out image signals and is able tothin out vertical components of the image signals to ½, ⅓, ¼, . . . tooutput the resulting thinned-out signals.

[0039] The S/H-A/D circuit 12 is also adapted to perform sample-holdingand A/D conversion at a pre-set sampling interval based on thesynchronization signals from the timing generator 13 to send theresulting image data to the signal processor 20.

[0040] The signal processor 20 includes a sole LSI (large scaleintegrated circuit). The signal processor 20 includes an input signalprocessor 21 for input processing and camera processing on image datafrom the image generating unit 10, a memory controller 22 forcontrolling the readout/write of image data for the image memory 32, anNTSC/PAL (phase alternation by line) encoder 23, a D/A converter 24 foranalogizing image data and outputting the resulting analog signals tooutside, and a sync generator 26 for generating synchronization signalsand supplying the resulting synchronization signals to the timinggenerator 13.

[0041] The signal processor 20 also includes a memory interface 27, asan interface for the image memory 32, a resolution conversion circuit 28for converting the resolution of the image data, a JPEG (JointPhotographic Experts Group) encoder/decoder 29, forcompressing/expanding image data, a JPEG interface 30, as an interfaceof the JPEG encoder/decoder 29, and a host interface 31, as an interfacefor having data transmission/reception with the CPU of the controller40.

[0042] The input signal processor 21 processes the image data from theS/H-A/D circuit 12 with digital clamp, shading correction, aperturecorrection, gamma correction or color processing and routes theresulting processed signals to the memory controller 22. The inputsignal processor 21 has the function of processing input data to convertthe input data into Y, Cb and Cr. If the resolution of the image data islarger than that of the VGA (Video Graphics Array), the input signalprocessor 21 is able to perform the processing of lowering theresolution. The input signal processor 21 also performs theauto-focussing and auto-iris detection to route the data to thecontroller 40 to effect automatic adjustment of the focussing mechanismand the iris mechanism. The input signal processor 21 also detects thesignal level of the three prime colors making up the image data toadjust automatic white balance.

[0043] The memory controller 22 also performs control to cause imagedata supplied from the input signal processor 21 or other circuitry tobe written in the image memory 32 via a memory interface 27 and to readout image data of the image memory 32 via the memory interface 27. Atthis time, the memory controller 22 detects whether or not there is anydefective pixel in the CCD image sensor 11 based on the image datastored in the image memory 32.

[0044] The memory controller 22 routes the image data read out from theimage memory 32 to, for example, the NTSC/PAL encoder 23. When fed withthe image data from the memory controller 22, the NTSC/PAL encoder 23encodes the image data in accordance with the NTSC system or the PALsystem to send the encoded data to the D/A converter 24. The D/Aconverter 24 analogizes the image data to output the resulting analogsignals via output terminal 25.

[0045] The memory controller 22 routes the image data, read out from thememory controller 22, to the resolution conversion circuit 28 to causethe image data to be converted in resolution, while causing the imagedata outputted by the resolution conversion circuit 28 to be written inthe image memory 32.

[0046] The memory controller 22 routes the image data via the JPEGinterface 30 to the JPEG encoder/decoder 29 to effect compression of thestill image, while causing the image data expanded by the JPEGencoder/decoder 29 to be written in the image memory 32.

[0047] The image memory 32 not only stores the image data as describedabove but also stores OSD data (on-screen-display data) as the so-calledcharacter generator data. The OSD data is made up of bit map data. Thecontroller 22 controls the readout/write of the OSD data. The image dataand the OSD data are synthesized by the NTSC/PAL encoder 23.

[0048] The controller 40 includes a CPU (central processing unit) 41 forcontrolling the respective circuits of the signal processor 20, a DRAM(dynamic random access memory) 42, a ROM (read-only memory) 43, havingthe control program for the CPU 41 stored therein, a flash memoryinterface 44, as an interface for exchanging image data with a storagedevice 51, such as a flash memory, and an IrDA interface 45, as aninterface of the communication circuit 52 constituted such as by IrLED.

[0049] For example, the CPU 41 causes image data compressed by the JPEGencoder/decoder 29 to be written via a flash memory/interface 44 in astorage device 51, made up of a flash memory, while causing image datato be read out from the storage device 51 to route the image data readout from the JPEG encoder/decoder 29. The CPU 41 also causes the imagedata read out from the storage device 51 to be outputted via the IrDAinterface 45 and the communication circuit 52 as infrared light tooutside.

[0050] The schematic structure of the digital still camera 1 is shown inFIG. 3.

[0051] The input signal processor 21 routes the image data from the CCDimage sensor 11 via an image data bus 33 to the image memory 32. TheNTSC/PAL encoder 23 encodes the image data from the image memory 32 in apre-set fashion to send the resulting encoded data to the finder 36.This causes an image of an object to be displayed on the finder 36 whichis adapted to display the image in association with the image data up tothe VGA format.

[0052] The memory controller 22 performs data transfer between the imagememory 32 and the signal processing circuits connecting to the imagedata bus 33. The resolution conversion circuit 28 performs resolutionconversion of the image data from the image memory 32 to route theresults to the image memory 32. The JPEG encoder/decoder 29 compressesthe image data from the image memory 32 in accordance with the JPEGsystem to route the compressed image data via CPU bus 34 to the CPU 41,which then causes the compressed image data to be written in the storagedevice 51. The CPU 41 is also able to output the compressed image datavia the CPU bus 34 and the communication circuit 52 to outside.

[0053] Thus, is FIG. 3, the respective circuits of the signal processor20 are interconnected over the image data bus 33. The image data bus 33is a virtual bus and indicates that there is placed a limit to thetransfer band for image data exchanged between the respective circuits.

[0054] In the signal processor 20, the respective circuits, such asNTSC/PAL encoder 23 or the resolution conversion circuit 28, send to thememory controller 22 a request signal indicating that image data aredemanded. These circuits also transmit a request signal to the memorycontroller 22 when outputting the image data after the end of theprocessing of the image data.

[0055] On reception of the request signals from the respective circuits,the memory controller 22 selects those circuits having the high prioritysequence, and transmits an acknowledge signal to the selected circuit.The acknowledge signal indicates that image data can be routed to acircuit receiving the signal or that image data outputted by a circuitwhich has received the acknowledge signal is ready to be received. Thememory controller 22 reads out image data from the image memory 32 toroute the read-out image data via image data bus 33 to the circuitcorresponding to the destination of the acknowledge signal. The memorycontroller 22 receives the image data outputted by the circuit which hassent the acknowledge signal to write the image data in the image memory32.

[0056] On reception of the request signals from plural circuits, thememory controller 22 is able to select preferentially the circuit whichhas to perform the processing in real-time. For example, if an image ofan object is to be displayed on the finder 36, the memory controller 22preferentially selects the input signal processor 21 and the NTSC/PALencoder 23. It is also possible for the memory controller 22 to decipherthe bus occupation ratio of the image data on the image data bus 33 todetermine the priority sequence of the respective circuits depending onthe occupation ratio.

[0057] If image data can be routed to the respective circuits within thetransfer band limitation of the image data bus 33, it is possible forthe memory controller 22 to perform control to send the acknowledgesignal to the respective circuits time-divisionally to permit therespective circuits to perform pre-set processing. This enables thememory controller 22 to have access in real-time to data in therespective circuits to cause the image data from the respective circuitsto be written in the image memory 32 or to cause the image data in theimage memory 32 to be read out and sent to the respective circuits.

[0058] If, when the memory controller 22 has access to externalcircuitry, not shown, over the image data bus 33, the external circuitrycan send the above-mentioned request signal or receive the transmittedacknowledge signal, the memory controller 22 can have accesssimultaneously and time-divisionally to the respective circuits withinthe signal processor 20 within the transfer band limitation range of theimage data bus 33. That is, if within the range of the band of the imagedata bus 33, the memory controller 22 can have simultaneous access tothe circuits in the signal processor 20 or to the external circuitswithin the signal processor 20 time-divisionally without regard to thenumber of the circuits within the signal processor 20 or the externalcircuit.

[0059] As mentioned above, the memory controller 22 performs arbitrationof the image data bus 33, write/readout control of image data betweenthe image memory 32 and the respective circuits and data transfer to theCPU bus 34.

[0060] The specified flow of image data in the signal processor 20 isexplained with reference to FIG. 4.

[0061] The input signal processor 21 includes a CCD interface 21 a forperforming preset signal processing on the image data from the imagegenerating unit 10, a detection circuit 21 b for processing the CCDinterface 21 a, and a camera digital signal processor 21 c (camera DSP21 c) for doing conversion processing of the image data.

[0062] The CCD interface 21 a performs the processing, such as thedigital clamp, white balance adjustment or gamma correction, on theimage data made up of R, G and B from the S/H-A/D circuit 12 showninformation FIG. 2, or decimates the components in the horizontaldirection of image data in case of necessity. After such processing, theCCD interface 21 a routes image data to the camera DSP 21 c or to thememory controller 22 via the image data bus 33.

[0063] From the image data of the CCD interface 21 a, the detectioncircuit 21 b performs detection for auto-focussing, auto-iris or whitebalance adjustment.

[0064] The camera DSP 21 c converts the image data of R, G and B fromthe CCD interface 21 a into image data made up of luminance signal Y andchrominance signals Cb, Cr. The camera DSP 21 c also has a simplifiedresolution conversion circuit 21 which not only performs the aboveprocessing but also converts the resolution of the image data in asimplified fashion.

[0065] The simplified resolution conversion circuit 21 d operates forconverting the resolution of the image data to lower values if theresolution of the image data generated by the CCD image sensor 11 islarger than, for example, the VGA format.

[0066] Specifically, the simplified resolution conversion circuit 21 dincludes a B-Y/R-Y separation circuit 61, for separating chrominancesignals, a horizontal direction linear interpolation circuit 62 forinterpolation in the horizontal direction, a B-Y/R-Y synthesis circuit63 for synthesizing the chrominance signals, a 1H delay circuit 64 fordelaying the respective signals by a horizontal scanning period (1Hperiod), and a vertical direction linear interpolation circuit 65.

[0067] The B-Y/R-Y separation circuit 61 separates the chrominancesignals B-Y and R-Y, as chroma signals Cb, Cr, from the image data fromthe camera DSP 21 c to route the separated chroma signals to thehorizontal direction linear interpolation circuit 62. The horizontaldirection linear interpolation circuit 62 interpolates the luminancesignals Y and the chrominance signals B-Y, R-Y in the horizontaldirection to lower the luminance in the horizontal direction to routethe interpolated luminance signals Y and the chrominance signals B-Y,R-Y to the B-Y/R-Y synthesis circuit 63.

[0068] The B-Y/R-Y synthesis circuit 63 synthesizes the chrominancesignals B-Y, R-Y, to route the luminance signals Y from the horizontaldirection linear interpolation circuit 62 and the synthesizedchrominance signals B-Y, R-Y to the 1H delay circuit 64 and to thevertical direction linear interpolation circuit 65. The 1H delay circuit64 delays the luminance signals Y and the chrominance signals by 1H toroute the delayed signals to the vertical direction linear interpolationcircuit 65. The vertical direction linear interpolation circuit 65performs linear interpolation processing in the vertical direction,based on the luminance signals Y and the chrominance B-Y, R-Y from theB-Y/R-Y synthesis circuit 63 and the 1H delay circuit 64, to outputimage data made up of luminance signals Y′ and chrominance signals(B-Y)′, (R-Y)′ lowered in resolution in both the horizontal and verticaldirections.

[0069] The resolution conversion circuit 28 performs resolutionconversion processing of converting [p×q] image data into [m×n] imagedata. The resolution conversion circuit 28 performs processing forsuppressing the resolution to a pre-set value if the image data producedin the CCD image sensor 11 are of high resolution. It is howeverpossible to process the image data of low resolution into data of highresolution.

[0070] Referring to FIG. 6, the resolution conversion circuit 28includes an input buffer 71 for storing image data, inputted from theimage data bus 33, a horizontal direction buffer 72, for buffering theimage data from the an input buffer 71 in the horizontal direction, ahorizontal direction transform processing circuit 73 for converting theresolution of the image data from the horizontal direction buffer 72 inthe horizontal direction, a vertical direction buffer 74 for bufferingthe image data from the horizontal direction transform processingcircuit 73 in the vertical direction, a vertical direction transformprocessing circuit 75 for converting the resolution of the image data inthe vertical direction, and an output buffer 76 for buffering at thetime of outputting.

[0071] When ready for converting the resolution of the image data, theresolution conversion circuit 28 outputs a read request signalrequesting the memory controller 22 to read out image data from theimage memory 32, while outputting a write request signal requesting thememory controller 22 to write the image data in the image memory 32after the conversion processing of the image data. The resolutionconversion circuit 28 also receives an acknowledge signal indicatingthat the memory controller 22 has responded to the request signal.

[0072] Referring to FIG. 7, the horizontal direction buffer 72 is madeup of a first delay circuit 81, a second delay circuit 82 and a thirddelay circuit 83 each for producing the delay of one pixel. Thus, thefirst delay circuit 81 outputs image data delayed by one pixel, whilethe second and third delay circuits 81, 82 output image data delayed bytwo pixels and image data delayed by three pixels, respectively.

[0073] Referring to FIG. 7, the horizontal direction transformprocessing circuit 73 includes first to fourth multipliers 84, 85, 86,87, and first to third adders 88, 89, 90. A circuit for normalizing datais incidentally annexed at back of the adder 90.

[0074] The first multiplier 84 multiplies the image data supplied fromthe an input buffer 71 with a pre-set coefficient to route the resultingdata to the adder 88. The second multiplier 85 multiplies the image datasupplied from the first delay circuit 81 with a pre-set coefficient toroute the resulting data to the adder 88. The third multiplier 86multiplies the image data supplied from the second delay circuit 82 witha pre-set coefficient to route the resulting data to the adder 89. Thefourth multiplier 87 multiplies the image data supplied from the thirddelay circuit 83 with a pre-set coefficient to route the resulting datato the adder 90. The first adder 88 synthesizes the image data to sendthe resulting data to the second adder 89. The second adder 89synthesizes the image data to send the resulting data to the third adder90. The third adder 90 synthesizes the respective image data to send theresulting data as image data converted in resolution in the horizontaldirection to the vertical direction buffer 74.

[0075] Thus, the horizontal direction transform processing circuit 73weights plural image data each having one pixel delay in a pre-setfashion with pre-set weights and synthesizes the weighted image data tointerpolate or decimate the pixels in the horizontal direction toconvert the resolution in the horizontal direction.

[0076] The vertical direction buffer 74 is constituted by a serialconnection of first to third buffers 91, 92, 93, each adapted to producea one-line delay. Thus, the first bufer memory 91 outputs image datadelayed by one line, while the second and third buffer memories 92, 93output the image data delayed by two and three lines, respectively.

[0077] Referring to FIG. 7, the vertical direction transform processingcircuit 75 includes fifth to eighth multipliers 94 to 97 and fourth tosixth adders 98 to 100. The vertical direction transform processingcircuit 75 occasionally includes a circuit for normalizing data on thedownstream side of the adder 90.

[0078] The fifth multiplier 94 multiplies the image data supplied fromthe horizontal direction conversion circuit 73 with a pre-setcoefficient to route the resulting data to the fourth adder 98. Thesixth multiplier 95 multiplies the image data supplied from the firstline memory 91 with a pre-set coefficient to route the resulting data tothe fourth adder 98. The seventh multiplier 96 multiplies the image datasupplied from the second line memory 92 with a pre-set coefficient toroute the resulting data to the fifth adder 99. The eighth multiplier 97multiplies the image data supplied from the third line memory 93 with apre-set coefficient to route the resulting data to the sixth adder 100.The fourth adder 98 synthesizes the image data to send the resultingdata to the fifth adder 99. The fifth adder 99 synthesizes the imagedata to send the resulting data to the sixth adder 100. The sixth adder100 synthesizes the respective image data to output the resulting dataas image data converted in resolution in the horizontal direction.

[0079] Thus, the vertical direction transform processing circuit 75weights plural image data each having one line delay in a pre-setfashion with pre-set weights and synthesizes the weighted image data tointerpolate or decimate the pixels in the horizontal direction toconvert the resolution in the vertical direction.

[0080] In FIG. 7, the resolution conversion circuit 28 first performsresolution conversion in the horizontal direction followed by resolutionconversion in the vertical direction. It is however possible for theresolution conversion circuit 28 to perform resolution conversion in thevertical direction followed by conversion in the horizontal direction.That is, the resolution conversion circuit 28 may be configured tosupply the image data from the input buffer 71 to the vertical directionbuffer 74 and to effect the processing in the vertical direction buffer74, vertical direction transform processing circuit 75, horizontaldirection buffer 72 and in the horizontal direction transform processingcircuit 73, in this order.

[0081] In the above-described embodiment, the first to third buffermemories 91 to 93 in the vertical direction buffer 74 are configured tostore one-line (1H) image data. Alternatively, the first to third buffermemories 91 to 93 may be configured for storing image data lesser thanone line, as shown in FIG. 9. It is then necessary for the memorycontroller 22 to read out the image data stored in the image memory 32every N pixels, as shown in FIG. 10.

[0082] Specifically, the memory controller 22 reads out pixel datacorresponding to a viewing screen stored in the image memory 32 every Npixels on the line basis in the vertical direction. Referring to FIG.11, each viewing screen is made up of p×q pixels, with the coordinate ofthe upper left pixel being (1,1), that of the upper right pixel being(p, 1), that of the lower left pixel being (1,q) and with the lowerright pixel being Referring to FIG. 12, the memory controller 22 causesthe image data ofN pixels to be read out on the line basis in thehorizontal direction in the sequence of the rows 1, 2, . . . , q. Thiscauses the memory controller 22 to read out image data corresponding toN pixels from the left end, or N×q pixels, that is pixel data in an areadefined by (1,1), (1,q), (N,q) and (N,1). This image data is referred tobelow as image data set (1).

[0083] The memory controller 22 then reads out image data in a rangedefined by (N−1,1) (N−1, q), (2N−2, q), (2N−2, 1), referred to below asthe image data set (2). If the memory controller 22 reads out the imagedata set (1) and the image data set (2), it is tantamount to reading outthe image data of the (N−1)st column and the Nth column twice.

[0084] The reason is that, since the vertical direction transformprocessing circuit 75 performs interpolation beginning from thesurrounding pixel, the pixels stored in the beginning end and thetrailing end of the first to third buffer memories 91 to 93 are not theobject of processing. For example, if the image data set (1) is readout, the pixel (N, 1) is not the object of the interpolation processingin the vertical direction. However, this pixel (N, 1) is read out whenthe pixel data set (2) is read out, and becomes the object ofinterpolation processing.

[0085] In similar manner, the memory controller 22 reads out image dataof N pixels in the horizontal direction every line so that image data ofthe last two columns of the directly previous image data set will beincluded. This routes the image data set to the resolution conversioncircuit 28.

[0086] The vertical direction buffer 74 is fed with image data, in anamount corresponding to the capacity of the first to third buffers 91 to93, on the line basis. Thus, image data offset one line is stored ineach f the first to third buffer memories 91 to 93. The verticaldirection transform processing circuit 75 is able to perform theresolution conversion processing in the vertical direction based on theimage data from the first to third buffers 91 to 93 of the verticaldirection buffer 74.

[0087] With the memory controller 22, the memory controller 22 can causethe resolution conversion circuit 28 to execute the resolutionconversion in the vertical direction, by readout in meeting with thecapacity of the buffer memory, even if the capacity of the buffer memoryrequired for resolution conversion in the vertical direction is not upto one line.

[0088] Although the read-out overlap between the image data sets is twocolumns, it is probable that the overlap exceeds two columns or there isno overlap. It is noted that the present invention is applicable toimage signal processing, such as camera signal processing, withoutlimitation to resolution conversion.

[0089] Although the foregoing description is directed to the embodimentin which the buffer memory is being used for interpolation for thevertical direction, the present invention is also applicable to anembodiment in which the buffer memory is being used for interpolationfor the horizontal direction.

[0090] That is, the resolution conversion circuit 28 may performresolution conversion in the horizontal direction using a horizontaldirection buffer 72 a comprised of a buffer memory 72 a having acapacity of N pixels, as shown in FIG. 13. The memory controller 22 canread out image data of N pixels on the column basis in the sequence ofthe rows 1, 2, . . . , p in the vertical direction, as shown in FIG. 14.Meanwhile, it is necessary for the memory controller 22 to read out theimage data stored at the leading and trailing ends of the buffer memorytwice, as in the above-described vertical interpolation processing, sothat these image data will be the object of the horizontal interpolationprocessing.

[0091] Thus, the memory controller 22 is able to read out image datafrom the image memory 32 so that resolution conversion processing in thehorizontal and vertical directions will be effected for the first tothird buffer memories 91 to 93 each having a capacity of N pixels. Thisenables the circuit scale of the horizontal direction buffer 72 and thevertical direction buffer 74 to be reduced to lower the production cost.

[0092] The NTSC/PAL encoder 23, executing the encoding as describedabove, also has a simplified resolution conversion circuit 23 a forincreasing the resolution of the image data, if need be, beforeproceeding to encoding.

[0093] The simplified resolution conversion circuit 23 a performsresolution conversion for matching to the display standard of the finder36 if the image data on the image memory 32 is lower than the resolutionrequired for display.

[0094] Referring to FIG. 15, the simplified resolution conversioncircuit 23 a includes a line memory 101 for storing image data from theimage data bus 33, a vertical direction linear interpolation circuit(V-direction linear interpolation circuit 102) for interpolating imagedata in the vertical direction, and a horizontal direction interpolationcircuit 103.

[0095] The line memory 101 stores image data from an input terminal inin an amount corresponding to one line to send the image data to theV-direction linear interpolation circuit 102 in the order it is stored.The V-direction linear interpolation circuit 102 weights the image datafrom the input terminal in and the image data from the V-directionlinear interpolation circuit 102 with a pre-set weighting to performlinear interpolation in the vertical direction. The horizontal directioninterpolation circuit 103 interpolates Y with an order-seven filter,while interpolating Cb and Cr with an order-three filter. This is simplythe interpolation for increasing the resolution by a factor of two. Thehorizontal direction interpolation circuit 103 outputs the image data atan output terminal out.

[0096] For example, if image data inputted from the input terminal in isdenoted a, image data read out from the line memory 101 is b, acoefficient for weighting is g, where 0≦g≦1, and image data outputted bythe V-direction linear interpolation circuit 102 is c, the V-directionlinear interpolation circuit 102 effectuates the following processing:

c=g*a+(1−g)*b.

[0097] The image data outputted by the output terminal out is encoded bythe NTSC/PAL encoder 23, as mentioned previously.

[0098] In the signal processing system, the digital still camera 1 ismade up of so-called two chips, namely s signal processor 20 and a CPU41. Therefore, the respective signal processing circuits are each of thechip configuration, so that the substrate surface area and further thepower consumption can be made smaller than if the respective signalprocessing circuits are of separate chip configurations.

[0099] Also, since the signal processor 20 is not of the chipconfiguration inclusive of the CPU, signal processing can be adaptivelyeffectuated even if the application in connection with the CPU 41 ischanged. That is, if the signal processor 20 is of the chipconfiguration inclusive of the CPU, it is impossible to reconstruct thechip in case the application of the CPU is changed. However, the signalprocessor 20 can perform the pre-set signal processing using a CPU of anoptimum structure on the application basis.

[0100] The digital still camera 1 of the above-described structure has afinder mode for confirming the status or the position of an object priorto image shooting, a recording mode for shooting the image of the objectas confirmed, and a reproducing mode for confirming the shot state ofthe object image, and effects the processing depending on the prevailingmode.

[0101] In the finder mode, the user has to observe the state of theobject indicated on the finder 36 before thrusting a shutter button, notshown, to shoot the object. In this finder mode, the memory controller22 and other circuits are controlled in the following manner. Forillustrating the respective modes, reference is had mainly to FIG. 4 andoccasionally to FIG. 16.

[0102] In the finder mode, the CCD image sensor 11 generates imagesignals, thinned out to one-third from the vertical components, andfurnishes the digitized image data via the S/H-A/D circuit 12 to the CCDinterface 21 a.

[0103] The CCD interface 21 a performs signal processing in synchronismwith clocks shown in FIG. 16A. Specifically, the CCD interface 21 adecimates the horizontal components of the image data supplied by theimage generating unit 10 to one-third and corrects the decimated imagedata for gamma to send the gamma-corrected data to the camera DSP 21 c.The CCD interface 21 a famishes the image data converted to 340×256 fromthe ⅓ decimation process to the camera DSP 21 c.

[0104] The camera DSP 21 c performs data conversion processing on thedecimated image data into YCrCb image data. The camera DSP 21 c convertsthe resolution of the image data in the simplified resolution conversioncircuit 21 d (340×256→320×240) for lowering the resolution of the imagedata to route the converted image data via image data bus 33 to thememory controller 22.

[0105] It is noted that the simplified resolution conversion circuit 21d lowers the resolution in a simplified fashion to an extent necessaryfor subsequent processing. In this manner, if image data generated bythe CCD image sensor 11 is of high resolution, the transfer range takenup by the image data generated by the CCD image sensor 11 can bedecreased to evade the stagnancy on the image data bus 33 to maintainthe real-time characteristics of the finder mode.

[0106] The memory controller 22 writes the image data in the imagememory 32, while reading out the image data from the image memory 32 asshown in FIG. 16D to send the read-out image data via the image data bus33 to the NTSC/PAL encoder 23. Simultaneously, the memory controller 22reads out the OSD data stored in the image memory 32, as shown in FIG.16E, to send the OSD data stored in the image memory 32, as shown inFIG. 16E. FIG. 16F shows the state of transfer on the image data bus 33which enables the above-described real-time processing.

[0107] The NTSC/PAL encoder 23 performs resolution conversion of320×240→640×240 or 320×240→640×288 in the case of the NTSC system or thePAL system, respectively, to send the converted image data to theNTSC/PAL encoder 23. The NTSC/PAL encoder 23 also converts the imagedata into data of the NTSC system or the PAL system into OSD data whichis routed to the finder 36 shown in FIG. 3. This allows the image of theobject and the title information etc to be displayed in-real time on thefinder 36.

[0108] Meanwhile, the NTSC/PAL encoder 23 converts the resolution sothat data with low resolution will be increased in resolution, suchthat, if 320×200 image data is furnished, it is converted into 640×240image data and into 640×288 image data for the NTSC system and for thePAL system, respectively.

[0109] In the digital still camera 1, the resolution of the image datagenerated by the CCD image sensor 11 is lowered in a simplified fashionin the finder mode to reduce the data volume, so that the image datawill be within the bandwidth limitation of the image data bus 33 and sothat the resolution will be increased at an output stage to the extentthat is necessary for display, at a timing shown in FIG. 16F.

[0110] Thus, with the digital still cameral, the image data is held inthe bandwidth limitation of the image data bus 33 to permit the image ofthe object to be displayed on the finder 36, even if the image data isof high resolution, without the necessity of performing thetime-consuming decimation processing.

[0111] If the circuitry for preferential processing, namely the CCDinterface 21 a, camera DSP 21 c or the NTSC/PAL encoder 23, ispreviously set in the CPU 41, and signal processing is carried outtime-divisionally in other circuits as in the above circuits, theprocessing of the respective circuits with high priority may bepreferentially performed depending on the data volume of the image data.

[0112] In the event of the large data volume of the image data in thesimplified resolution conversion circuit 21 d, data processing may beperformed at a high processing speed, in order to give priority toreal-time processing, even though the picture quality is degraded to acertain extent, under control by the CPU 41. In this manner, high-speedprocessing can be effected in the finder mode even in case of the largedata volume of the image data generated in the image generating unit 10.

[0113] In the case of the digital still camera 1, having an electroniczooming function, the CPU 41 can control the respective circuits in thefollowing manner.

[0114] The memory controller 22 causes the image data, supplied via theCCD interface 21 a and camera DSP 21 c, to be written in the imagememory 32, while causing the image data to be read out from the imagememory 32 and routed to the resolution conversion circuit 28. Theresolution conversion circuit 28 formulates image data enlarged from aportion of the input image, by an electronic zooming function, to outputthe resulting image data to the image memory 32. This image data is readout from the image memory 32 and outputted to the finder 36 via theNTSC/PAL encoder 23. This generates electronically zoomed image data.

[0115] Since the finder mode gives utmost priority to the real-timecharacteristics, time-consuming processing is not executed by therespective circuits. However, the CPU 41 can be configured to cause thememory controller 22 and other circuits to perform various processingoperations if within the range allowed by the transfer area of the imagedata bus 33.

[0116] For example, the memory controller 22 may be configured to readout image data from the image memory 32, in which is stored the imagedata furnished from the CCD interface 21 a, and to furnish the read-outimage data to the NTSC/PAL encoder 23 over the image data bus 33 and tothe JPEG encoder/decoder 29. The finder 36 displays the image of theobject in rea-time, while the JPEG encoder/decoder 29 compresses theimage data in accordance with the JPEG system.

[0117] The JPEG encoder/decoder 29 compresses/expands the still image,while it cannot process high-pixel image in real-time. It is thuspossible for the JPEG encoder/decoder 29 to decimate a pre-set number offrames of the image data supplied from the image data bus 33 (number offrames or fields) by way of compression or to slice a portion of theimage to lower the resolution by way of compression. This enablesshooting of a frame-decimated still image continuously or shooting of alow-resolution image continuously.

[0118] The user observes the state of the object displayed on the finder36 in the above-mentioned finder mode. If the object is decided to beshot, the user pushes a shutter button, not shown.

[0119] If the shutter button is pushed, the digital still camera 1proceeds to the recording mode. In the recording mode, the CPU 41controls the memory controller 22 or the respective circuits in thefollowing manner to record the image of the as-shot object on arecording device 51.

[0120] The CCD image sensor 11 halts the decimation operation insynchronism with the thrusting the shutter button to generate imagesignals of the XGA format to route the digitized image data via theS/H-A/D circuit 12 to the CCD interface 21 a.

[0121] The CCD interface 21 a routes the image data furnished from theS/H-A/D circuit 12 not to the camera DSP 21 c, but to the memorycontroller 22 via the image data bus 33. The memory controller 22 firstwrites the image data in the image memory 32 and subsequently reads outthe image data to route the read-out image data via the image data bus33 to the camera DSP 21 c. The camera DSP 21 c converts the image datamade up of RGB into image data made up of Y, Cb and Cr.

[0122] The camera DSP 21 c is fed with image data once written in theimage memory 32. That is, the camera DSP 21 c effects data conversion onthe image data from the image memory 32 instead of on the image datadirectly supplied from the CCD interface 21 a. Thus, it is unnecessaryfor the camera DSP 21 c to perform high-speed data conversion, but it isonly sufficient if the camera DSP 21 c executes such processing when theimage data bus 33 is not busy. Stated differently, it is unnecessary forthe camera DSP 21 c to perform the processing in real-time, so that dataconversion processing can be executed with priority given to the highpicture quality rather than to the high processing speed and theresulting converted image data may be routed to the memory controller 22via the image data bus 33. The memory controller 22 causes the imagedata to be written in the image memory 32.

[0123] The memory controller 22 causes the image data to be read outfrom the image memory 32 to route the read-out image data to the JPEGencoder/decoder 29. The JPEG encoder/decoder 29 compresses the imagedata in accordance with the JPEG system to write the compressed imagedata in the recording device 51 shown in FIG. 3.

[0124] If real-time processing is not unnecessary, as during recording,the CPU 41 permits the pre-set processing to be executed after writingthe image data transiently in the image memory 32 to exploit thetransfer band of the image data bus 33 to process the high-pixel image.

[0125] The CPU 41 records the image data of the XGA format directly inthe recording device 51 in the recording mode. It is however possiblefor the resolution conversion circuit 28 to convert the resolution ofthe image data before recording the image data on the recording device51. Specifically, it is possible to cause the resolution conversioncircuit 28 to convert the resolution of the image data read out from theimage memory 32 via the memory controller 22 in meeting with the VGA(1024×768→640×480) to permit the JPEG encoder/decoder 29 to compress theimage data to record the compressed data in the recording device 51.

[0126] If desirous to confirm the as-shot image after image shooting,the operator thrusts the playback button, not shown, for reproducing theas-shot image.

[0127] If the reproducing button is thrust, the digital still camera 1moves to the reproducing mode. In the reproducing mode, the CPU 41controls the respective circuits in the following manner to read out theimage data of the object.

[0128] That is, on detecting the thrusting the reproducing button, theCPU 41 reads out the image data from the recording device 51 andtransiently stores the read-out image data in the DRAM 42 before routingthe data via CPU bus 34 to the JPEG encoder/decoder 29. The JPEGencoder/decoder 29 expands the image data read out from the recordingdevice 51 in accordance with the JPEG system to produce image data ofthe XGA format to route the resulting image data via the image data bus33 to the memory controller 22.

[0129] The memory controller 22 writes the image data on the imagememory 32 and reds out the image data from the image memory 32 to sendthe read-out image data via the image data bus 33 to the resolutionconversion circuit 28.

[0130] The resolution conversion circuit 28 effects resolutionconversion so that the image data will be in meeting with the VGA format(1024×768→640×480 in the NTSC system and 1024×768→640×576 in the PALsystem) to route the converted image data over the image data bus 33 tothe memory controller 22. The image data then is read from the imagememory 32 and routed via the NTSC/PAL encoder 23 to the finder 36. Thisdisplays an image corresponding to the image data recorded in therecording device 51 on the finder 36.

[0131] That is, since the image data recorded in the recording device 51has high resolution, the CPU 41 first lowers the resolution andsubsequently routes the image data to the finder 36.

[0132] It is also possible for the CPU 41 to set, for each of the findermode, recording mode and the reproducing mode, the order of priority ofthe circuits to be processed in preference and to cause the pertinentcircuit to execute the processing in accordance with the order ofpriority on movement to one of the modes. This enables the signalprocessing of image data to be executed efficiently depending on theprocessing contents in each mode.

[0133] In the above-described embodiment, it is assumed that the databeing processed is the image data equivalent to XGA. It is to be notedthat the present invention is not limited to this embodiment and can beapplied to, for example, the processing of image data comprised of onemillion or more pixels.

What is claimed is:
 1. A signal processing apparatus comprising: storagemeans for storing image data; control means for controlling thewriting/readout of the image data for said storage means; and aplurality of signal processing means for processing the image data in apre-set fashion and for outputting to said control means a requestsignal for demanding furnishment of the image data for the signalprocessing or demanding the outputting of the processed image data; saidcontrol means managing control on furnishment of said request signal toselect one or more of said signal processing means which has outputtedsaid request signal, to furnish the image data read out from the storagemeans to the selected signal processing means or to write the image dataoutputted by the selected signal processing means in said storage means.2. The signal processing apparatus according to claim 1 wherein saidplural signal processing means includes respective timing generatingmeans.
 3. The signal processing apparatus according to claim 1 furthercomprising: an image data bus arranged between said control means andthe signal processing means for transmitting/receiving said image data.4. The signal processing apparatus according to claim 1 wherein saidcontrol means preferentially selects the signal processing meansrequired to perform signal processing in real-time.
 5. The signalprocessing apparatus according to claim 1 wherein the apparatus includesa plurality of processing modes and wherein said control means sets theorder of priority of said plural signal processing means responsive tosaid operating modes.
 6. The signal processing apparatus according toclaim 3 wherein said control means manages control so that the imagedata will be within the range of a transfer band of the image data bus.7. The signal processing apparatus according to claim 1 wherein saidcontrol means selects a plurality of signal processing means from thesignal processing means time-divisionally and simultaneously.
 8. Thesignal processing apparatus according to claim 1 wherein said controlmeans outputs an acknowledge signal indicating the effect of selectionto the selected signal processing means; said signal processing meansafter receiving said acknowledge signal exchanging image data with saidcontrol means.
 9. A controlling method for a signal processing apparatusadapted for transmitting/receiving image data between a plurality ofsignal processing means and storage means adapted for storing imagedata, said signal processing means being adapted for processing theimage data in a pre-set fashion and for outputting to said control meansa request signal demanding furnishment of the image data for signalprocessing or demanding the outputting of the processed image data,comprising: selecting, on furnishment of said request signal from saidplural signal processing means, one or more of said signal processingmeans which has outputted said request signal; and furnishing the imagedata read out from the storage means to the selected signal processingmeans or writing the image data outputted by the selected signalprocessing means in said storage means.
 10. The control method accordingto claim 9 wherein said plural signal processing means output saidrequest signals based on timing generating means owned individually bysaid signal processing means.
 11. The control method according to claim9 wherein transmission/reception of said image data is via an image databus.
 12. The control method according to claim 9 wherein the signalprocessing means required to be processed in real-time is preferentiallyselected.
 13. The control method according to claim 9 wherein the signalprocessing apparatus has a plurality of operating modes; and wherein theorder of priority of said plural signal processing means is setresponsive to said operating mode.
 14. The control method according toclaim 11 wherein control is performed so that the image data will becomprised within the transfer band of said image data bus.
 15. Thecontrol method according to claim 9 wherein the plural signal processingmeans are selected simultaneously time-divisionally.
 16. The signalprocessing method according to claim 9 wherein an acknowledge signalindicating the effect of selection is outputted to the selected signalprocessing means; said signal processing means after receiving saidacknowledge signal exchanging image data with said control means.
 17. Animaging apparatus comprising: imaging means; storage means fortransiently storing image data from said imaging means; control meansfor controlling the writing/readout of said image data for said storagemeans; a plurality of signal processing means for processing the imagedata in a pre-set fashion and for outputting to said control means arequest signal demanding furnishment of the image data for signalprocessing or demanding the outputting of the processed image data; andoutputting means for outputting image data processed by said signalprocessing means; said control means managing control on furnishment ofsaid request signal to select one or more of said signal processingmeans which has outputted said request signal, to furnish the image dataread out from the storage means to the selected signal processing meansor to write the image data outputted by the selected signal processingmeans in said storage means.
 18. The imaging apparatus according toclaim 17 comprising, as said signal processing means: display processingmeans for performing processing to display said image data on displaymeans; and recording processing means for performing processing torecord said image data on a recording medium; said control meanspreferentially selecting said display processing means.
 19. Arecording/reproducing apparatus comprising: imaging means; inputprocessing means for performing pre-set input processing on image datafrom said imaging means; display processing means for displaying imagedata on display means; first storage means for transiently storing theimage data from said imaging means; control means for controlling thewriting/readout of the image data for said first storage means;resolution converting means for converting the resolution of image data;compression/expansion means for compressing/expanding the image data;and recording/reproducing controlling means for causing the compressedimage data to be recorded on second storage means and for causing theimage data recorded on said second storage means to be reproduced; saidcontrol means selecting one or more signal processing means from saidinput processing means, display processing means, resolution convertingmeans and said compression/expansion means, said control means causingthe image data read out from the first storage means to be sent to theselected signal processing means or causing the image data outputted bythe selected signal processing means to be written in the first storagemeans.
 20. The recording/reproducing apparatus according to claim 19having a finder mode for displaying image data from said imaging meanson said display means, a recording mode for recording the image data onsaid second recording means, and a reproducing mode for reproducing theimage data from said second storage means; said control means settingthe order of priority of said plural signal processing means responsiveto said respective modes.
 21. The recording/reproducing apparatusaccording to claim 20 wherein said control means preferentially selectsthe input processing means and the display processing means if the modeis the finder mode.